Contains the settings for the schematics.

ERC

This section includes the set of rules used for the automatic check of the schematic and for the generation of the netlist.

ERC active during wire drawing: Specify whether the ERC (Electrical Rules Check) control should be active during the drawing of the electrical schematics. If this option is enabled, a message is displayed when a connection violates the ERC settings.

Compiling Netlist

This section includes options for compiling the netlist.

Connection modes in Multi-Sheet projects

When a schematic is divided into multiple pages, the following options determine how connections are made between the pins of components belonging to different pages.

The scope of the Net

Connections can be limited to the page or extended to the whole project:

Page	Connection names are only valid within the page where they are defined. All connections with the same name belonging to the same page are always linked together. Connections with the same name but belonging to different pages are not linked together.
Project	The names of the connections are valid on all pages of the project. All connections with the same name belonging to the same page or different pages are linked together. Connections whose name is determined by a hidden pin always have global validity.

Note:
Connections whose name is determined by a hidden pin, such as VCC and GND power connections, are always globally valid.

The scope of the Port

The ports allow you to extend a connection so as to connect to each other electrical terminals not connected by a wire. Ports can have a validity limited to the page or extended to the whole project:

Page	Ports names are only valid within the page where they are defined. All Ports with the same name belonging to the same page are always linked together. Ports with the same name but belonging to different pages are not linked together.
Project	The names of the Ports are valid in all pages of the project. All Ports with the same name belonging to the same page or different pages are linked together.

Defining connection names

During the generation of the netlist, each connection is automatically assigned a name except in cases where one of the following objects is connected to the connection: Net Label, Bus Entry, Hidden Pin, Power Port. The following options determine how the connection name is to be constructed.

Use the name of the Port

The connection can take its name from the name of the Port.

Use the name of the Sheet Port

The connection can take its name from the name of the Sheet Port.

Use the name of the Pin

The connection can take its name from the name of the Pin. The full name is formed by the prefix Net followed by the reference of the component to which the pin belongs and the name of the pin. For example, NetQ2_E detects the connection relative to the emitter of the Q2 transistor.

Use the number of the Pin

The connection can take its name from the number of the Pin. The full name is formed by the prefix Net followed by the reference of the component to which the pin belongs and the pin number. For example, NetU2_1 detects the connection to pin 1 of the U2 component.

The names of the connections always in the form N00000

The name of the connection is determined by a five-digit sequential number preceded by the character N.

Correct the names of the connections

Removes, from net names, characters that could cause problems in SPICE simulations. In particular, it operates the following substitutions:

Replace	With
+	_P_
-	_N_
*	_M_
/	_D_

The replacement is performed only for the netlist generated for the simulation.

Violations

This section presents all possible violations that may occur in a schematic. For each violation you can specify the level of severity associated with the violation. For each violation detected, a message is generated in the Messages.

Tip:
To generate only error messages, activate the Report only errors option.

ERC matrix

This section displays a connection matrix through which you can establish connectivity rules between component pins, ports, and sheet entry. The matrix defines the logical or electrical conditions that must be reported as warnings or errors. For example, an output pin connected to another output pin is normally an error condition, unlike the connection between two passive pins. For each violation detected, a message is generated in the Messages.

The matrix allows you to check all possible connections between the Pins, Ports and Sheet Entry and also any unconnected elements. The color of each cell indicates the type of signaling that will be generated for the connection between the elements identified by the row and column that intersect in the cell. To change the reporting mode for a connection, simply click on the colored square in which the row and column of two elements intersect. Each time you click, the mode will move to the next reporting level.

Tip:
To return all elements of the matrix to their default value, click the Restore button.