A Bus line is a path to which terminals (Bus Entry objects) can be connected for the input and output of electrical signals. A Bus allows you to enclose multiple connections in a single graphic symbol, simplifying the design and reading of a schematic. For example, in the following figure, the Bus line connected to the CPUADDR port contains the 16 connections relative to the addressing bits of the EPROM, while the Bus line connected to the CPUDATA port contains the 8 connections relative to the data bits.
Input and output of signals from the Bus
Bus Entry objects must be used for the input and output of signals from the Bus. An object of type Bus Entry represents a terminal for the input and output of signals from a Bus and is represented with a 45ยบ line attached to the outer edge of the Bus. A Bus Entry object assigns its name to the connection for which it is not necessary to name with a Net Label a connection in which there is a Bus Entry object.
Extension of Bus lines
In multi-page schematics, Bus lines can be extended between the pages of a project by simply connecting them to a Port. You can specify which signals are to be propagated by the Port by attaching an object Net Label to the Bus segment to which the Port is connected. In the absence of an explicit indication, the Port propagates all the signals present in the Bus.
Connections in the Bus
Since the input lines to the Bus are nominal, it is not necessary to specify the signals propagated by the Bus. The Bus, in fact, propagates all the signals detected by the Bus Entry objects hooked to the Bus.
The only case in which it may be necessary to explicitly indicate the signals present in the Bus is when the Bus is connected to a bus type pin. A pin with bus functionality represents several pins of a component with a single graphic symbol. This pin type allows you to create simplified symbols in which all pins corresponding to data or address lines are represented with a single pin.
In the following figure, the address Bus is divided into two branches and in each of them a Net Label object is added with the explicit indication of the signals that must be connected with the pins of the components. All signals must be homogeneous, i.e. all signals must have the same prefix. The order in which the signals are read is from left to right. The connections obtained in the example are as follows:
In component U2: Signal A0 is connected to pin AD0, signal A1 is connected to pin AD1, etc.
In component U3: signal A8 is connected to pin AD0, signal A9 is connected to pin AD1, etc.
The CPUADDR port propagates all signals from A0 to A15.
