The digital RAM is an M-wide, N-deep random access memory element with
programmable select lines, tristated data_out lines, and a single write/read
line. The depth of the RAM (N) is set by the number of address lines input
to the device. The value of N is related to the number of address input
lines (P) by the following equation: 2p=N.
There is no reset line into the device. However, an initial value for all
bits may be specified by setting the ic parameter to either 0 or 1. In
reading a word from the ram, the read_delay value is invoked, and output
will not appear until that delay has been satisfied. Separate rise and fall
delays are not supported for this device.
Note that UNKNOWN inputs
on the address lines are not allowed during a write. In the event that an
address line does indeed go unknown during a write, THE ENTIRE CONTENTS OF
THE RAM WILL BE SET TO UNKNOWN. This is in contrast to the data_in lines
being set to unknown during a write; in that case, only the selected word
will be corrupted, and this is corrected once the data lines settle back to
a known value. Note that protection is added to the write_en line such that
extended UNKNOWN values on that line are interpreted as ZERO values. This is
the equivalent of a read operation and will not corrupt the contents of the
RAM. A similar mechanism exists for the select lines. If they are unknown,
then it is assumed that the chip is not selected.
Detailed
timing-checking routines are not provided in this model, other than for the
enable_delay and select_delay restrictions on read operations. You are
advised, therefore, to carefully check the timing into and out of the RAM
for correct read and write cycle times, setup and hold times, etc. for the
particular device they arc attempting to model.