The digital open-emitter is a simple open-emitter gate. The state seen on
the input line is reflected in the output. The state seen on the input line
determines the strength of the output. If the input to this device is a 1,
then the output is a 1 with a STRONG. If the input is a 0, then the output
is a HI_IMPEDANCE 0, otherwise, the output strength is UNDETERMINED. The
falling (open_delay) and rising (rise_delay) delays may be specified
independently.